GLOBALFOUNDRIES INC.

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Technologies

Intl Class Technology MATTERS Rank in Class
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 9783 3
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 3129 23
 
 
G11C STATIC STORES 740 18
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 435 10
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 427 13
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 281 94
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 257 22
 
 
H03K PULSE TECHNIQUE 237 23
 
 
G01N INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES 167 60
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM 142 43
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Top Patents (by citation)

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0033,590 STRUCTURE AND METHOD TO MEASURE FOCUS-DEPENDENT PATTERN SHIFT IN INTEGRATED CIRCUIT IMAGING Jul 28, 16 Feb 01, 18 [H01J]
2018/0033,700 METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT Oct 10, 17 Feb 01, 18 [H01L]
2018/0033,701 METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE Oct 09, 17 Feb 01, 18 [G06F, H01L]
2018/0033,718 INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD Jul 27, 16 Feb 01, 18 [H01L]
2018/0033,726 PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF Oct 04, 17 Feb 01, 18 [H01L]
2018/0033,728 IC STRUCTURE WITH INTERFACE LINER AND METHODS OF FORMING SAME Jul 28, 16 Feb 01, 18 [H01L]
2018/0033,789 METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES Jul 29, 16 Feb 01, 18 [H01L]
2018/0033,863 METHODS OF FORMING AN AIR-GAP SPACER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE Aug 01, 16 Feb 01, 18 [H01L]
2018/0033,870 PREVENTING BRIDGE FORMATION BETWEEN REPLACEMENT GATE AND SOURCE/DRAIN REGION THROUGH STI STRUCTURE Jul 26, 16 Feb 01, 18 [H01L]
2018/0033,871 METHODS OF FORMING IC PRODUCTS COMPRISING A NANO-SHEET DEVICE AND A TRANSISTOR DEVICE Jul 26, 16 Feb 01, 18 [H01L]
2018/0025,483 METHODS OF DETECTING FAULTS IN REAL-TIME FOR SEMICONDUCTOR WAFERS Jul 19, 16 Jan 25, 18 [G06T, G06K]
2018/0025,929 SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION Jul 25, 16 Jan 25, 18 [G05B, H01L]
2018/0025,936 LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES Jul 20, 16 Jan 25, 18 [H01L]
2018/0026,028 METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS Apr 06, 17 Jan 25, 18 [H01L]
2018/0026,096 SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE Jul 22, 16 Jan 25, 18 [H01L]
2018/0026,113 FIN-BASED RF DIODES Jun 07, 17 Jan 25, 18 [H01L]
2018/0026,580 SWITCHED CAPACITOR CIRCUIT STRUCTURE WITH METHOD OF CONTROLLING SOURCE-DRAIN RESISTANCE ACROSS SAME Jul 19, 16 Jan 25, 18 [H03B]
2018/0016,699 ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION Sep 19, 17 Jan 18, 18 [C25D]
2018/0019,147 CENTERING FIXTURE FOR ELECTROSTATIC CHUCK SYSTEM Jul 12, 16 Jan 18, 18 [H01L, B25J]
2018/0019,162 AMORPHOUS CARBON LAYER FOR COBALT ETCH PROTECTION IN DUAL DAMASCENE BACK END OF THE LINE INTEGRATED CIRCUIT METALLIZATION INTEGRATION Jul 13, 16 Jan 18, 18 [H01L]
2018/0019,214 WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE Jul 24, 17 Jan 18, 18 [H01L]
2018/0019,241 METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES Jul 12, 16 Jan 18, 18 [H01L]
2018/0019,305 STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB) Sep 27, 17 Jan 18, 18 [H01L]
2018/0019,313 COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME Sep 28, 17 Jan 18, 18 [H01L]
2018/0019,337 METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET Aug 22, 17 Jan 18, 18 [H01L]
2018/0012,647 METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS Sep 21, 17 Jan 11, 18 [G11C, H01L]
2018/0012,648 STATIC RANDOM ACCESS MEMORY (SRAM) ASSIST CIRCUIT Jul 07, 16 Jan 11, 18 [G11C]
2018/0012,760 DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC Aug 11, 17 Jan 11, 18 [H01L]
2018/0012,791 INTERCONNECTS WITH INNER SACRIFICIAL SPACERS Jul 06, 16 Jan 11, 18 [H01L]
2018/0012,798 METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUCTOR ACTIVE REGION HAVING HIGH-K DIELECTRIC GATE CAPS Aug 29, 17 Jan 11, 18 [H01L]
2018/0012,805 SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS Sep 08, 17 Jan 11, 18 [H01L]
2018/0012,812 HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION Aug 02, 17 Jan 11, 18 [H01L]
2018/0012,813 ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING Jul 05, 16 Jan 11, 18 [G05B, G03F, G06F, H01L]
2018/0012,839 INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME Jul 11, 16 Jan 11, 18 [H01L]
2018/0012,845 SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION Sep 25, 17 Jan 11, 18 [H01L]
2018/0012,877 DIE-DIE STACKING Sep 22, 17 Jan 11, 18 [H01L]
2018/0012,887 METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR Jul 06, 16 Jan 11, 18 [H01L]
2018/0012,895 STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO Sep 14, 17 Jan 11, 18 [H01L]
2018/0012,973 DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI Sep 21, 17 Jan 11, 18 [H01L]
2018/0012,988 DUAL STRESS DEVICE AND METHOD Aug 16, 17 Jan 11, 18 [H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9881122 Overlay sampling reduction Mar 30, 16 Jan 30, 18 [G03F, G06F]
9881669 Wordline driver with integrated voltage level shift function Mar 01, 17 Jan 30, 18 [G11C]
9881738 Capacitor structures with embedded electrodes and fabrication methods thereof Aug 05, 15 Jan 30, 18 [H01G, H01L]
9881830 Electrically insulated fin structure(s) with alternative channel materials and fabrication methods Jan 06, 15 Jan 30, 18 [H01L]
9881841 Methods for fabricating integrated circuits with improved implantation processes Mar 18, 16 Jan 30, 18 [H01L]
9882024 Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins Nov 28, 16 Jan 30, 18 [H01L]
9882025 Methods of simultaneously forming bottom and top spacers on a vertical transistor device Sep 30, 16 Jan 30, 18 [H01L]
9882052 Forming defect-free relaxed SiGe fins Jun 30, 16 Jan 30, 18 [H01L]
9882081 Photodetector methods and photodetector structures Aug 03, 16 Jan 30, 18 [H01L]
9874690 Integrated waveguide structure with perforated chip edge seal Oct 04, 13 Jan 23, 18 [G02B]
9875334 Generating manufacturable sub-resolution assist feature shapes from a usefulness map May 16, 16 Jan 23, 18 [G03F, G06F]
9875905 FinFET devices having fins with a tapered configuration and methods of fabricating the same Oct 22, 15 Jan 23, 18 [H01L]
9875936 Spacer defined fin growth and differential fin width Nov 10, 16 Jan 23, 18 [H01L]
9875939 Methods of forming uniform and pitch independent fin recess Dec 08, 16 Jan 23, 18 [H01L]
9875940 Methods for forming transistor devices with different threshold voltages and the resulting devices Aug 07, 15 Jan 23, 18 [H01L]
9875956 Integrated interface structure Sep 26, 16 Jan 23, 18 [H01L]
9876010 Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure Nov 03, 16 Jan 23, 18 [H01L]
9876077 Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices Jun 30, 16 Jan 23, 18 [H01L]
9876089 High-k and p-type work function metal first fabrication process having improved annealing process flows Jun 15, 16 Jan 23, 18 [H01L]
9876111 Method of forming a semiconductor device structure using differing spacer widths and the resulting semiconductor device structure Apr 05, 16 Jan 23, 18 [H01L]
9870163 Double bandwidth algorithmic memory array Apr 27, 16 Jan 16, 18 [G06F]
9870936 Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication Feb 04, 16 Jan 16, 18 [B08B, H01L]
9870942 Method of forming mandrel and non-mandrel metal lines having variable widths Jan 19, 17 Jan 16, 18 [H01L]
9871020 Through silicon via sharing in a 3D integrated circuit Jul 14, 16 Jan 16, 18 [G11C, H01L]
9871050 Flash memory device Aug 10, 16 Jan 16, 18 [H01L]
9871057 Field-effect transistors with a non-relaxed strained channel Mar 03, 16 Jan 16, 18 [H01L]
9871096 Serial capacitor device with middle electrode contact Mar 15, 17 Jan 16, 18 [H01L]
9871531 Non-geometric scaling current steering digital to analog converter Jan 23, 17 Jan 16, 18 [H03M]
9864132 Silicon waveguide devices in integrated photonics Sep 30, 16 Jan 09, 18 [G02B, H01L]
9864136 Non-planar monolithic hybrid optoelectronic structures and methods Aug 09, 16 Jan 09, 18 [G02B, H01L]
9864831 Metrology pattern layout and method of use thereof Mar 16, 16 Jan 09, 18 [G03F, G06F]
9865392 Solenoidal series stacked multipath inductor Jun 13, 14 Jan 09, 18 [H01F]
9865473 Methods of forming semiconductor devices using semi-bidirectional patterning and islands Nov 15, 16 Jan 09, 18 [H01L]
9865486 Timing/power risk optimized selective voltage binning using non-linear voltage slope Mar 29, 16 Jan 09, 18 [G01R, G06F, H01L]
9865514 Inline measurement of through-silicon via depth Mar 10, 15 Jan 09, 18 [H01L]
9865543 Structure and method for inhibiting cobalt diffusion Jan 26, 17 Jan 09, 18 [H01L]
9865546 Contacts to semiconductor substrate and methods of forming same Jun 03, 15 Jan 09, 18 [H01L]
9865564 Laser ashing of polyimide for semiconductor manufacturing Feb 18, 15 Jan 09, 18 [B08B, B23K, B32B, H01L]
9865570 Integrated circuit package with thermally conductive pillar Feb 14, 17 Jan 09, 18 [H01L]
9865603 Transistor structure having N-type and P-type elongated regions intersecting under common gate Mar 19, 15 Jan 09, 18 [H01L]
9865608 Method of forming a device including a floating gate electrode and a layer of ferroelectric material May 23, 16 Jan 09, 18 [H01L]
9865681 Nanowire transistors having multiple threshold voltages Mar 08, 17 Jan 09, 18 [H01L]
9865682 Directed self-assembly material etch mask for forming vertical nanowires Sep 04, 14 Jan 09, 18 [H01L, B82Y]
9865704 Single and double diffusion breaks on integrated circuit products comprised of FinFET devices May 31, 16 Jan 09, 18 [H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2017/0330,878 NOVEL METHOD TO FABRICATE VERTICAL NWs ABAN May 13, 16 Nov 16, 17 [H01L]
2017/0294,354 INTEGRATION OF NOMINAL GATE WIDTH FINFETS AND DEVICES HAVING LARGER GATE WIDTH ABAN Apr 07, 16 Oct 12, 17 [H01L]
2017/0207,118 SELF-ALIGNED SOURCE/DRAIN CONTACT IN REPLACEMENT METAL GATE PROCESS ABAN Jan 14, 16 Jul 20, 17 [H01L]
2017/0162,430 METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AIR GAPS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS ABAN Dec 03, 15 Jun 08, 17 [H01L]
2017/0154,687 SRAM-LIKE EBI STRUCTURE DESIGN AND IMPLEMENTATION TO CAPTURE MOSFET SOURCE-DRAIN LEAKAGE EARILER ABAN Nov 30, 15 Jun 01, 17 [G11C, H01L]
2017/0125,288 ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS ABAN Jan 17, 17 May 04, 17 [H01L]
2017/0077,234 DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS ABAN Sep 14, 15 Mar 16, 17 [H01L]
2017/0069,518 ELECTROSTATIC SUBSTRATE HOLDER WITH NON-PLANAR SURFACE AND METHOD OF ETCHING ABAN Sep 04, 15 Mar 09, 17 [H01L]
2017/0033,061 MITIGATING TRANSIENT TSV-INDUCED IC SUBSTRATE NOISE AND RESULTING DEVICES ABAN Jul 29, 15 Feb 02, 17 [H01L]
2017/0033,181 METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS ABAN Jul 28, 15 Feb 02, 17 [H01L]
2017/0025,347 METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION ABAN Feb 12, 16 Jan 26, 17 [H01L]
2017/0019,982 METHOD, APPARATUS AND SYSTEM FOR PROVIDING MULTIPLE EUV BEAMS FOR SEMICONDUCTOR PROCESSING ABAN Jul 18, 15 Jan 19, 17 [G21K, H05G]
2016/0377,448 PREDICTING AND ALERTING USER TO NAVIGATION OPTIONS AND PREDICTING USER INTENTIONS ABAN Jun 29, 15 Dec 29, 16 [G06N, G01C]
2016/0379,818 INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE ABAN Jun 25, 15 Dec 29, 16 [H01L]
2016/0380,067 SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR ABAN Jun 23, 15 Dec 29, 16 [H01L]
2016/0380,095 HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION ABAN Jun 25, 15 Dec 29, 16 [H01L]
2016/0372,413 UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME ABAN Jun 17, 15 Dec 22, 16 [H01L]
2016/0351,675 INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES ABAN May 26, 15 Dec 01, 16 [H01L]
2016/0336,172 LITHOGRAPHY STACK AND METHOD ABAN May 14, 15 Nov 17, 16 [G03F, H01L]
2016/0329,278 2D SELF-ALIGNED VIA FIRST PROCESS FLOW ABAN Apr 21, 16 Nov 10, 16 [H01L]

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