EASIC CORPORATION

Patent Owner

Watch Compare Add to Portfolio

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H03K PULSE TECHNIQUE 15116
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 14348
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 6441
 
 
 
G11C STATIC STORES 4147
 
 
 
H01H ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES 193
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 1284

Top Patents (by citation)

Upgrade to the Professional Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0293,541 STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA LAYERSApr 01, 15Oct 06, 16[H01L]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9704874 ROM segmented bitline circuitDec 09, 15Jul 11, 17[H01L, G11C]
RE46474 Multiple write during simultaneous memory access of a multi-port memory deviceDec 22, 14Jul 11, 17[G11C]
9024657 Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smallerOct 11, 12May 05, 15[H03K, G06F]
8957398 Via-configurable high-performance logic block involving transistor chainsOct 11, 12Feb 17, 15[H03K, H01L, G06F]
8848479 Multiple write during simultaneous memory access of a multi-port memory deviceMar 24, 11Sep 30, 14[G11C]
8735857 Via-configurable high-performance logic block architectureOct 12, 11May 27, 14[H01L]
8677306 Microcontroller controlled or direct mode controlled network-fabric on a structured ASICOct 11, 12Mar 18, 14[G06F]
8629548 Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic nodeOct 11, 12Jan 14, 14[H01L]
8504865 Dynamic phase alignmentApr 20, 07Aug 06, 13[H04L, G06F]
8436700 MEMS-based switchingSep 18, 09May 07, 13[H01H]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0124,899 MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATIONAbandonedMay 22, 15May 05, 16[G06F]
2014/0103,985 Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed InterfaceAbandonedOct 11, 12Apr 17, 14[H03H]
2014/0105,246 Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic NodeAbandonedOct 11, 12Apr 17, 14[G01K]
2010/0182,044 PROGRAMMING AND CIRCUIT TOPOLOGIES FOR PROGRAMMABLE VIASAbandonedMar 26, 10Jul 22, 10[H03K]
2007/0187,808 Customizable power and ground pinsAbandonedFeb 16, 06Aug 16, 07[H01L]
2006/0176,075 Customizable and Programmable Cell ArrayAbandonedApr 03, 06Aug 10, 06[H03K]
2006/0033,124 Method for fabrication of semiconductor deviceAbandonedOct 03, 05Feb 16, 06[H01L]
2005/0167,701 Method for fabrication of semiconductor deviceAbandonedApr 04, 05Aug 04, 05[H01L]
6823499 Method for designing application specific integrated circuit structureExpiredSep 16, 02Nov 23, 04[G06F, G00F]

Top Inventors for This Owner

Upgrade to the Professional Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.